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Preliminary Technical Data
Table 8. UART Timing (Shift Register Mode) Parameters
4.096 MHz Core Clock
ADE7566/ADE7569
Variable Core Clock
Parameter
t XLXL
Description
Serial port clock cycle time
Min
Typ Max
2.93
Min
Typ Max
12 × t CORE 1
Unit
μs
t QVXH
t DVXH
t XHDX
t XHQX
Output data setup to clock
Input data setup to clock
Input data hold after clock
Output data hold after clock
TBD
TBD
TBD
TBD
μs
μs
μs
μs
1
t CORE depends on the clock divider or CD bits of the POWCON SFR, t CORE = 2 CD /4.096 MHz.
TxD
(OUTPUT CLOCK)
t XLXL
t QVXH
t XHQX
SET RI
OR
SET TI
RxD
(OUTPUT DATA)
LSB
BIT 1
t DVXH
t XHDX
BIT 6
RxD
(INPUT DATA)
LSB
BIT 1
BIT 6
MSB
Figure 8. UART Timing in Shift Register Mode
Rev. PrA | Page 15 of 136
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